![]() ![]() The 24-bit "Bus A" is used for general accesses, while the 8-bit "Bus B" is used for support chip registers (mainly the video and audio processors). The chip has an 8-bit data bus, controlled by two address buses. ![]() Only the controller port serial-access registers use the divisor of 12. ![]() WRAM accesses and other general accesses use the divisor of 8. Non-access cycles, most register accesses, and some general accesses use the divisor of 6. The CPU employs a variable bus speed depending on the memory region being accessed for each instruction cycle: the input clock is divided by 6, 8, or 12 to obtain the bus clock rate. The CPU is a Nintendo-custom 5A22 processor, based on a 16-bit 65c816 core.
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